1. Field of the Invention
The present invention relates to a gain variable circuit that can operate at low voltage relative to a differential signal, and to an automatic gain control amplifier (hereafter, “AGC amp”) using the same.
2. Related Art
Conventionally-known technologies relating to gain variable circuits are known, for example, the technologies recited in the following publications:
Non-patent Publication 1: M. Moller, H. -M. Rein and H. Wernz, “13 Gb/s Si-Bipolar AGC Amplifier IC with High Gain and Wide Dynamic Range for Optical-Fiber Receivers”, IEEE Journal of Solid-state Circuits, Vol. 29, No. 7, July 1994, pp. 815-822; and
Patent Publication 1: JP-A No. 9-18329.
In FIG. 2(a) on p. 817 of Non-patent Publication 1, a circuit diagram of a gain variable circuit formed from bipolar transistors is disclosed. The circuit diagram of an AGC amp using this gain variable circuit is disclosed in FIG. 1 on p. 816 of the same publication.
Further, in FIG. 3 of Patent Publication 1, the circuit configuration diagram of a Gilbert-type multiplier (a double balanced-type differential amplifier) that uses an electric field effect transistor (hereafter “FET”) of the same circuit configuration as the gain variable circuit of Non-patent Publication 1 is disclosed. This multiplier is a circuit into which two analog signals are inputted and which then outputs an output signal that proportions the product of these. Its applications differ from that of a gain variable circuit.
FIG. 4 is a circuit diagram showing a conventional gain variable circuit.
This gain variable circuit is a circuit in which the gain variable circuit formed from the bipolar transistor recited in Non-patent Publication 1 is replaced with an FET in order to simplify the explanations.
The gain variable circuit of FIG. 4 has: a positive-phase signal input terminal IN; a reverse-phase signal input terminal INB; a positive-phase signal output terminal OUT; a reverse-phase signal output terminal OUTB; gain variable terminals VGC1, VGC2; and a supply terminal VD. Between these terminals, two load resistors 1, 2 and seven FETs 11-17 are connected.
One of terminals of each of the load resistors 1, 2 is connected to the supply terminal VD. The other terminal of the load resistor 1 and the drains of the FETs 11, 13 are connected to the output terminal OUTB, and the other terminal of the load resistor 2 and the drains of the FETs 12, 14 are connected to the output terminal OUT. The gates of the FETs 11, 14 are connected to the gain variable terminal VGC1 and the gates of the FETs 12, 13 are connected to the gain variable terminal VGC2. The sources of the FETs 11, 12 are connected to the drain of the FET 15 and the sources of the FETs 13, 14 are connected to the drain of the FET 16. The gate of the FET 15 is connected to the input terminal IN and the gate of the FET 16 is connected to the input terminal INB. The sources of the FETs 15, 16 are connected to the drain of the FET 17 and the gate and the source of this FET 17 are connected to the ground GND.
With this gain variable circuit, the constant current source is formed from the FET 17, the differential circuit for signal amplification is formed from the FETs 15 and 16, and the differential circuit for gain variation is formed from FETs 11-14.
In this type of circuit configuration, the FET 15 and 16 are made to have the same characteristics, and each of the FET 11, 12, 13, 14 are made to have the same characteristics.
Here, the input signal voltage applied to the positive-phase signal input terminal IN is vin and the input signal voltage applied to the reverse-phase signal input terminal INB is −vin, and the difference of the gain variable voltage applied to the gain variable terminals VGC1 and VGC2 is vgc. The constant current that flows to the FET 17 drain is i, the resistance value of load resistors 1 and 2 is r, the drain current dependency of the reciprocal conductance of the FET 15 and 16 is A1, and the drain current dependency of the reciprocal conductance of each of the FET 11, 12, 13, 14 is A2.
Drain current I15 of the FET 15 is derived by:
                                                                        I                ⁢                                                                  ⁢                15                            =                              i                ·                                                      [                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                                                                                    {                                                              vin                                -                                                                  (                                                                      -                                    vin                                                                    )                                                                                            }                                                        /                            2                                                                                                                ]                                    /                  2                                                                                                        =                              i                ·                                                      (                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                          vin                                                                                      )                                    /                  2                                                                                        (        1        )            
Drain current I16 of the FET 16 is derived by:
                                                                        I                ⁢                                                                  ⁢                16                            =                              i                ·                                                      [                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                                                                                    {                                                                                                (                                                                      -                                    vin                                                                    )                                                                -                                vin                                                            }                                                        /                            2                                                                                                                ]                                    /                  2                                                                                                        =                              i                ·                                                      (                                          1                      -                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                          vin                                                                                      )                                    /                  2                                                                                        (        2        )            
Drain current I11 of the FET 11 is derived by:
                                                                        I                ⁢                                                                  ⁢                11                            =                              I                ⁢                                                                  ⁢                                  15                  ·                                                            (                                              1                        +                                                  A                          ⁢                                                                                                          ⁢                                                      2                            ·                                                          vgc                              /                              2                                                                                                                          )                                        /                    2                                                                                                                          =                              i                ·                                  (                                      1                    +                                          A                      ⁢                                                                                          ⁢                                              1                        ·                        vin                                                                              )                                ·                                                      (                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  2                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  4                                                                                        (        3        )            
Drain current I12 of the FET 12 is derived by:
                                                                        I                ⁢                                                                  ⁢                12                            =                              I                ⁢                                                                  ⁢                                  15                  ·                                                            (                                              1                        -                                                  A                          ⁢                                                                                                          ⁢                                                      2                            ·                                                          vgc                              /                              2                                                                                                                          )                                        /                    2                                                                                                                          =                              i                ·                                  (                                      1                    +                                          A                      ⁢                                                                                          ⁢                                              1                        ·                        vin                                                                              )                                ·                                                      (                                          1                      -                                              A                        ⁢                                                                                                  ⁢                                                  2                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  4                                                                                        (        4        )            
Drain current I13 of the FET 13 is derived by:
                                                                        I                ⁢                                                                  ⁢                13                            =                              I                ⁢                                                                  ⁢                                  16                  ·                                                            (                                              1                        -                                                  A                          ⁢                                                                                                          ⁢                                                      2                            ·                                                          vgc                              /                              2                                                                                                                          )                                        /                    2                                                                                                                          =                              i                ·                                  (                                      1                    +                                          A                      ⁢                                                                                          ⁢                                              1                        ·                        vin                                                                              )                                ·                                                      (                                          1                      -                                              A                        ⁢                                                                                                  ⁢                                                  2                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  4                                                                                        (        5        )            
Drain current I14 of the FET 14 is derived by:
                                                                        I                ⁢                                                                  ⁢                14                            =                              I                ⁢                                                                  ⁢                                  16                  ·                                                            (                                              1                        +                                                  A                          ⁢                                                                                                          ⁢                                                      2                            ·                                                          vgc                              /                              2                                                                                                                          )                                        /                    2                                                                                                                          =                              i                ·                                  (                                      1                    -                                          A                      ⁢                                                                                          ⁢                                              1                        ·                        vin                                                                              )                                ·                                                      (                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  2                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  4                                                                                        (        6        )            
Further, the current I11 flowing to the load resistor 1 is the sum of the FET 11's drain current I11 and the FET 13's drain current I13, and that value becomes as follows due to Equations (3) and (5);
                                                                        I                ⁢                                                                  ⁢                1                            =                                                I                  ⁢                                                                          ⁢                  11                                +                                  I                  ⁢                                                                          ⁢                  13                                                                                                        =                              i                ·                                                      (                                          1                      -                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                          A                                                ⁢                                                                                                  ⁢                                                  2                          ·                          vin                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  2                                                                                        (        7        )            
The current I2 flowing to the load resistor 2 is the sum of the FET 12's drain current I12 and the FET 14's drain current I14, and that value becomes as follows due to Equations (4) and (6):
                                                                        I                ⁢                                                                  ⁢                2                            =                                                I                  ⁢                                                                          ⁢                  12                                +                                  I                  ⁢                                                                          ⁢                  14                                                                                                        =                              i                ·                                                      (                                          1                      +                                              A                        ⁢                                                                                                  ⁢                                                  1                          ·                          A                                                ⁢                                                                                                  ⁢                                                  2                          ·                          vin                          ·                                                      vgc                            /                            2                                                                                                                )                                    /                  2                                                                                        (        8        )            
Accordingly, if the change from the time where the vout vgc=0 of the output signal voltage outputted from the positive-phase signal output terminal OUT is made Δ vout, then Δ vout becomes:Δvout=r·A1·A2·vin vgc/4  (9)
The change from the time where the voutb vgc=0 of the output signal voltage outputted from the reverse-phase signal output terminal OUTB is made Δ voutb, then Δ voutb becomes:Δvoutb=−r·A1·A2·vin·vgc/4  (10)
In this manner, the circuit configured as described above operates as a gain variable circuit where the gain is varied by the difference vgc of the voltage applied to the gain variable terminal VGC1 and VGC2. Further, the FET 17 for constant current supply is provided. For this reason, even if, for example, the input signal voltage −vin applied to the reverse-phase signal input terminal INB is made into fixed voltage and the input signal voltage vin applied to the positive-phase signal input terminal IN is made into variable voltage, there is the advantageous point that a single pulse conversion function of the differential circuits for signal amplification that are the FET 15 and 16 works and stabilized line-form output voltage can be obtained.
Nonetheless, the conventional gain variable circuit comprises three tiers of vertical stacking of the FET 17 for constant current supply, the FET 15 and 16 of differential circuits for signal amplification, and the FETs 11-14 of the differential circuits for gain variation, as well as the load resistors 1 and 2. For this reason, there are a large number of elements, or, in order to power the FETs, the voltage between the necessary drain sources is made Vds and the voltage applied to the load resistors 1, 2 is made Vr, whereby the minimum supply voltage Vmin necessary becomes as follows:Vmin=3·Vds+Vr 
This is problematic in that it is difficult to lower the power supply voltage lower than this.
The gain variable circuit is used when configuring various integrated circuits such as AGC amps and the like so, especially in this case, the above problem becomes a big obstacle in reducing the supply power voltage to the integrated circuits and curtailing the number of configured elements. Solving this problem has been difficult.